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? semiconductor components industries, llc, 2010 january, 2010 ? rev. 3 1 publication order number: nb6l295/d nb6l295 2.5v / 3.3v dual channel programmable clock/data delay with differential lvpecl outputs multi ? level inputs w/ internal termination the nb6l295 is a dual channel programmable delay chip designed primarily for clock or data de ? skewing and timing adjustment. the nb6l295 is versatile in that two individual variable delay channels, pd0 and pd1, can be configured in one of two operating modes, a dual delay or an extended delay. in the dual delay mode, each channel has a programmable delay section which is designed using a matrix of gates and a chain of multiplexers. there is a fixed minimum delay of 3.2 ns per channel. the extended delay mode amounts to the additive delay of pd0 plus pd1 and is accomplished with the serial data interface msel bit set high. this will internally cascade the output of pd0 into the input of pd1. therefore, the extended delay path starts at the in0/in0 inputs, flows through pd0, cascades to the pd1 and outputs through q1/q1 . there is a fixed minimum delay of 6 ns for the extended delay mode. the required delay is accomplished by programming each delay channel via a 3 ? pin serial data interface, described in the application section. the digitally selectable delay has an increment resolution of typically 11 ps with a net programmable delay range of either 0 ns to 6 ns per channel in dual delay mode; or from 0 ns to 11.2 ns for the extended delay mode. the multi ? level inputs can be driven directly by differential lvpecl, lvds or cml logic levels; or by single ended lvpecl, lvcmos or lvttl. a single enable pin is available to control both inputs. the sdi input pins are controlled by lvcmos or lvttl level signals. the nb6l295 lvpecl output contains temperature compensation circuitry. this device is offered in a 4 mm x 4 mm 24 ? pin qfn pb ? free package. the nb6l295 is a member of the eclinps max ? family of high performance products. ? input clock frequency > 1.5 ghz with 550 mv v outpp ? input data rate > 2.5 gb/s ? programmable delay range: 0 ns to 6 ns per delay channel ? programmable delay range: 0 ns to 11.2 ns for extended delay mode ? total delay range: 3.2 ns to 8.8 ns per delay channel ? total delay range: 6 ns to 17 ns in extended delay mode ? monotonic delay: 11 ps increments in 511 steps ? linearity 20 ps, maximum ? 100 ps typical rise and fall times ? 3 ps typical clock jitter, rms ? 20 ps pk ? pk typical data dependent jitter ? lvpecl, cml or lvds differential input compatible ? lvpecl, lvcmos, lvttl single ? ended input compatible ? 3 ? wire serial interface ? operating range: v cc = 2.375 v to 3.6 v ? lvpecl output level; 780 mv peak ? to ? peak, typical ? internal 50 input termination provided ? ? 40 c to 85 c ambient operating temperature ? 24 ? pin qfn, 4 mm x 4 mm ? these are pb ? free devices* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagram* http://onsemi.com qfn ? 24 mn suffix case 485l a = assembly location l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on p age 13 of this data sheet. ordering information nb6l 295 alyw 1 24 24 1
nb6l295 http://onsemi.com 2 figure 1. simplified functional block diagram 256 gd* 0 1 0 1 128 gd* 64 gd* 32 gd* 16 gd* 8 gd* 4 gd* 2 gd* 1 gd* 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 256 gd* 0 1 0 1 128 gd* 64 gd* 32 gd* 16 gd* 8 gd* 4 gd* 2 gd* 1 gd* 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 psel msel d0 d1 d2 d3 d4 d5 d6 d7 d8 9 bit latch 9 bit latch 11 bit shift register sdata sclk sload *gd = gate delay *gd = gate delay pd1 pd0 vt0 vt0 50 50 50 50 in0 in0 vt1 vt1 in1 in1 q0 q0 q1 q1 en
nb6l295 http://onsemi.com 3 sdin sload vcc vt1 vcc0 q0 vcc0 vcc1 q1 vcc1 gnd vt1 vcc vt0 gnd en sclk in0 in1 in1 in0 q1 q0 vt0 nb6l295 18 12 4 3 5 6 789 11 10 2 1 17 16 15 14 13 19 24 23 22 20 21 exposed pad (ep) figure 2. pinout: qfn ? 24 (top view) table 1. pin description pin name i/o description 1 vcc power supply positive supply voltage for the inputs and core logic 2 en lvcmos/lvttl input input enable/ disable for both pd0 and pd1. low for enable, high for disable, open pin default state low (37 k pulldown resistor). 3 sload lvcmos/lvttl input serial load; this pin loads the configuration latches with the contents of the shift register. the latches will be transparent when this signal is high; thus, the data must be stable on the high ? to ? low transition of s_load for proper operation. open pin default state low (37 k pulldown resistor). 4 sdin lvcmos/lvttl input serial data in; this pin acts as the data input to the serial configuration shift register. open pin default state low (37 k pulldown resistor). 5 sclk lvcmos/lvttl input serial clock in; this pin serves to clock the serial configuration shift register. data from sdin is sampled on the rising edge. open pin default state low (37 k pulldown resistor). 6 vcc power supply positive supply voltage for the inputs and core logic 7 vt1 internal 50 termination pin for in1 8 in1 lvpecl, cml, lvds input non ? inverted differential input. note 1. 9 in1 lvpecl, cml, lvds input inverted differential input. note 1. 10 vt1 internal 50 termination pin for in1 11 gnd power supply negative power supply 12 vcc1 power supply positive supply voltage for the q1/q1 outputs, channel pd1 13 q1 lvpecl output inverted differential output. channel 1. typically terminated with 50 resistor to v cc1 ? 2.0 v. 14 q1 lvpecl output non ? inverted differential output. c hannel 1. t ypically terminated with 50 resistor to v cc1 ? 2.0 v. 15 vcc1 power supply positive supply voltage for the q1/q1 outputs, channel pd1 16 vcc0 power supply positive supply voltage for the q0/q0 outputs, channel pd0 17 q0 lvpecl output inverted differential output. channel 0. typically terminated with 50 resistor to v cc0 ? 2.0 v. 18 q0 lvpecl output non ? inverted differential output . c hannel 0. t ypically terminated with 50 resistor to v cc0 ? 2.0 v. 19 vcc0 power supply positive supply voltage for the q0/q0 outputs, channel pd0 20 gnd power supply negative power supply 21 vt0 internal 50 termination pin for in0 22 in0 lvpecl, cml, lvds input inverted differential input. note 1. 23 in0 lvpecl, cml, lvds input noninverted differential input. note 1. 24 vt0 internal 50 termination pin for in0 ? ep ground the exposed pad (ep) on the qfn ? 24 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to gnd and must be connected to gnd on the pc board. 1. in the differential configuration when the input termination pin (vtx/vtx ) are connected to a common termination voltage or left open, and if no signal is applied on inx/inx input then the device will be susceptible to self ? oscillation. 2. all vcc, vcc0 and vcc1 pins must be externally connected to the same power supply for proper operation. both vcc0s are connec ted to each other and both vcc1s are connected to each other: vcc0 and vcc1 are separate.
nb6l295 http://onsemi.com 4 table 2. attributes characteristics value input default state resistors 37 k esd protection human body model machine model > 2 kv > 100v moisture sensitivity (note 3) qfn ? 24 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 3094 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc , v cc0 , v cc1 positive power supply gnd = 0 v 4.0 v v io positive input/output voltage gnd = 0 v ? 0.5 v io v cc + 0.5 4.5 v v inpp differential input voltage |inx ? inx | v cc ? gnd v i in input current through r t (50 resistor) 50 ma i out output current (lvpecl output) continuous surge 50 100 ma ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm qfn ? 24 qfn ? 24 37 32 c/w c/w jc thermal resistance (junction ? to ? case) (note 4) qfn ? 24 11 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb6l295 http://onsemi.com 5 table 4. dc characteristics, multi ? level inputs v cc = v cc0 = v cc1 = 2.375 v to 3.6 v, gnd = 0 v, t a = ? 40 c to +85 c symbol characteristic min typ max unit power supply current i cc power supply current (inputs, v tx and outputs open) (sum of i cc , i cc0 , and i cc1 ) 110 140 170 ma lvpecl outputs (notes 5 and 6, figure 21) v oh output high voltage v cc = v cc0 = v cc1 = 3.3 v v cc = v cc0 = v cc1 = 2.5 v v cc ? 1075 2225 1425 v cc ? 950 2350 1550 v cc ? 825 2475 1675 mv v ol output low voltage v cc = v cc0 = v cc1 = 3.3 v v cc ? 1825 1475 v cc ? 1725 1575 v cc ? 1625 1675 mv v cc = v cc0 = v cc1 = 2.5 v v cc ? 1825 675 v cc ? 1725 775 v cc ? 1600 900 differential input driven single ? ended (see figures 10 and 11) (note 7) v th input threshold reference voltage range 1050 v cc ? 150 mv v ih single ? ended input high voltage v th + 150 v cc mv v il single ? ended input low voltage gnd v th ? 150 mv v ise single ? ended input voltage amplitude (v ih ? v il ) 300 v cc ? gnd mv differential inputs driven differentially (see figures 12 and 13) (note 8) v ihd differential input high voltage 1200 v cc mv v ild differential input low voltage gnd v cc ? 150 mv v id differential input voltage swing (inx, inx ) (v ihd ? v ild ) 150 v cc ? gnd mv v cmr input common mode range (differential configuration) (note 9) 950 v cc ? 75 mv i ih input high current inx/inx , (vtn/vtn open) ? 150 150 a i il input low current in/inx , (vtn/vtn open) ? 150 150 a single ? ended lvcmos/lvttl control inputs v ih single ? ended input high voltage 2000 v cc mv v il single ? ended input low voltage gnd 800 mv i ih input high current ? 150 150 a i il input low current ? 150 150 a termination resistors r tin internal input termination resistor 40 50 60 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. lvpecl outputs loaded with 50 to v cc ? 2.0 v for proper operation. 6. input and output parameters vary 1:1 with v cc . 7. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. v th is applied to the complementary input when operating in single ? ended mode. 8. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 9. v cmr (min) varies 1:1 with voltage on gnd pin, v cmr (max) varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal.
nb6l295 http://onsemi.com 6 table 5. ac characteristics v cc = v cc0 = v cc1 = 2.375 v to 3.6 v, gnd = 0 v, t a = ? 40 c to +85 c (note 10) symbol characteristic unit min typ max f sclk serial clock input frequency, 50% duty cycle 20 mhz v outpp output voltage amplitude (@ v inppmin ) f in 1.5 ghz (note 15) (see figure 22) 530 780 mv f data maximum data rate (note 14) 2.5 gb/s t range programmable delay range (@ 50 mhz) dual mode in0/in0 to q0/q0 or in1/in1 to q1/q1 extended mode in0/in0 to q1/q1 0 0 5.7 11.2 6.9 13.7 ns t skew duty cycle skew (note 11) within device skew ? dual mode d[8:0] = 0 d[8:0] = 1 0 2 60 60 5 100 175 ps l in linearity (note 12) 15 20 ps t s setup time (@ 20 mhz) sdin to sclk sload to sclk en to sdin 0.5 1.5 0.5 0.3 1.0 ns t h hold time sdin to sclk sload to sclk en to sload 1.0 1.0 0.5 0.6 ns t pwmin minimum pulse width sload 1 ns t jitter random clock jitter rms; setmin to setmax (note 13) f in 1.5 ghz dual mode in0/in0 to q0/q0 or in1/in1 to q1/q1 extended mode in0/in0 to q1/q1 deterministic jitter; setmin to setmax (note 14) f data 2.5 gbps dual mode in0/in0 to q0/q0 or in1/in1 to q1/q1 3 6 20 10 20 30 ps v inpp input voltage swing/sensitivity (differential configuration) (note 15) 150 v cc ? gnd mv t r, t f output rise/fall times (@ 50 mhz), (20% ? 80%) qx, qx 85 120 170 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. measured by forcing v inppmin and v inppmax from a 50% duty cycle clock source, v cmr (min+max). all loading with an external r l = 50 to v cc . see figure 20. input edge rates 40 ps (20% ? 80%). 11. duty cycle skew is measured between differential outputs using the deviations of the sum of t pw ? and t pw + @ 0.5 ghz. 12. deviation from a linear delay (actual min to max) in the dual mode 511 programmable steps. 13. additive random clock jitter with 50% duty cycle input clock signal. 14. nrz data at prbs23 and k28.5. 15. input and output voltage swing is a single ? ended measurement operating in differential mode.
nb6l295 http://onsemi.com 7 table 6. ac characteristics v cc = v cc0 = v cc1 = 2.375 v to 3.6 v, gnd = 0 v, ta = ? 40 c to +85 c (note 16) symbol characteristic ? 40 c +25 c +85 c unit min typ max min typ max min typ max t plh , t phl propagation delay (@ 50 mhz) dual mode in0/in0 to q0/q0 or in1/in1 to q1/q1 d[8:0] = 0 d[8:0] = 1 extended mode iin0/in0 to q1/q1 d[8:0] = 0 d[8:0] = 1 2.7 7.2 5.0 14.2 2.9 8.0 5.5 15.2 3.2 8.8 6.0 17.1 2.8 7.5 5.2 14.8 3.1 8.4 5.8 16.5 3.4 9.3 6.3 18.2 2.9 7.9 5.5 15.6 3.2 9.2 6.2 16.4 3.6 9.9 6.8 19.6 ns t step delay (selected d bit high all others low) d0 high d1 high d2 high d3 high d4 high d5 high d6 high d7 high d8 high 9.6 19.4 40 81 167 338 678 1358 2715 8.7 19 42 85 175 355 714 1432 2861 11 24.4 52 99 196 389 774 1544 3074 ns note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16. measured by forcing v inppmin and v inppmax from a 50% duty cycle clock source, v cmr (min+max). all loading with an external r l = 50 to v cc . see figure 20. input edge rates 40 ps (20% ? 80%).
nb6l295 http://onsemi.com 8 serial data interface programming the nb6l295 is programmed by loading the 11 ? bit shift register using the sclk, sdata and sload inputs. the 11 sdata bits are 1 psel bit, 1 msel bit and 9 delay value data bitsd[8:0]. a separate 11 ? bit load cycle is required to program the delay data value of each channel, pd0 and pd1. for example, at powerup two load cycles will be needed to initially set pd0 and pd1; dual mode operation as shown in figures 3 and 4 and extended mode operation as shown in figures 5 and 6. dual mode operations pd0 programmable delay control bits value pd1 programmable delay control bits value 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 1 d8 d7 d6 d5 d4 d3 d2 d1 d0 msel psel bit name d8 d7 d6 d5 d4 d3 d2 d1 d0 msel psel bit name (msb) (lsb) name (msb) (lsb) name figure 3. pdo shift register figure 4. pd1 shift register extended mode operations pd0 programmable delay control bits value pd1 programmable delay control bits value 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 d8 d7 d6 d5 d4 d3 d2 d1 d0 msel psel bit name d8 d7 d6 d5 d4 d3 d2 d1 d0 msel psel bit name (msb) (lsb) name (msb) (lsb) name figure 5. pdo shift register figure 6. pd1 shift register refer to table 7, channel and mode select bit functions. in a load cycle, the 11 ? bit shift register least significant bit (clocked in first) is psel and will determine which channel delay buffer, either pdo (low) or pd1 (high), will latch the delay data value d[8:0]. the msel bit determines the delay mode. when set low, the dual delay mode is selected and the device uses both channels independently. a pulse edge entering in0/in0 is delayed according to the values in pd0 and exits from q0/q0 . an input signal pulse edge entering in1/in1 is delayed according to the values in pd1 and exits from q1/q1 . when msel is set high, the extended delay mode is selected and an input signal pulse edge enters in0 and in0 and flows through pd0 and is extended through pd1 to exit at q1 and q1 . the most significant 9 ? bits, d[8:0] are delay value data for both channels. see figure 7. table 7. channel and mode select bit functions bit name function psel 0 loads data to pd0 1 loads data to pd1 msel 0 selects dual programmable delay paths, 3.1 ns to 8.8 ns delay range for each path 1 selects extended delay path from in0/in0 to q1/q1 , 6.0 ns to 17.2 ns delay range; disables q0/q0 outputs, q0 ? low, q0 ? high. d[8:0] select one of 512 delay values
nb6l295 http://onsemi.com 9 d8 d7 d6 d5 d4 d3 d2 d1 d0 msel psel figure 7. serial data interface, shift register, data latch, programmable delay channels d8 d7 d6 d5 d4 d3 d2 d1 d0 d8 d7 d6 d5 d4 d3 d2 d1 d0 01 pd1 latch pd0 latch pd0 delay pd1 delay sload q1/q1 q0/q0 sdata sclk 11 ? bit shift register msel serial data interface loading loading the device through the 3 input serial data interface (sdi) is accomplished by sending data into the sdin pin by using the sclk input pin and latching the data with the sload input pin. the 11 ? bit shift register shifts once per rising edge of the sclk input. the serial input sdin must meet setup and hold timing as specified in the ac characteristics section of this document for each bit and clock pulse. the sload line loads the value of the shift register on a low ? to ? high edge transition (transparent state) into a data latch register and latches the data with a subsequent high ? to ? low edge transition. further changes in sdin or sclk are not recognized by the latched register. the internal multiplexer states are set by the psel and msel bits in the shift register. figure 6 shows the timing diagram of a typical load sequence. input en should be low (enabled) prior to sdi programming, then pulled high (disabled) during programming. after programming, the en should be returned low (enabled) for functional delay operation. sdin sclk sload lsb en msb psel msel d0 d1 d2 d3 d4 d5 d6 d7 d8 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 figure 8. sdi timing diagram t s sdin to sclk t h sdin to sclk t s sclk to sload t pwmin
nb6l295 http://onsemi.com 10 table 8 shows theoretical values of delay capabilities in both the dual delay mode and in the extended delay modes of operation. table 8. examples of theoretical delay values for pd0 and pd1 in dual mode inputs: in0/in0 , in1/in1 , outputs: q0/q0 , q1, q1 dual mode pd0 delay* (ps) pd1 delay* (ps) pd1 d[8:0] (decimal) pd0 d[8:0] (decimal) msel 000000000 (0) 000000000 (0) 0 0 0 000000000 (0) 000000001 (1) 0 11 0 000000000 (0) 000000010 (2) 0 22 0 000000000 (0) 000000011 (3) 0 33 0 000000000 (0) 000000100 (4) 0 44 0 000000000 (0) 000000101 (5) 0 55 0 000000000 (0) 000000110 (6) 0 66 0 000000000 (0) 000000111 (7) 0 77 0 000000000 (0) 000001000 (8) 0 88 0 ? ? ? ? ? ? ? ? ? 000000000 (0) 000010000 (16) 0 176 0 000000000 (0) 000100000 (32) 0 352 0 000000000 (0) 001000000 (64) 0 704 0 000000000 (0) 111111101 (509) 0 5599 0 000000000 (0) 111111110 (510) 0 5610 0 000000000 (0) 111111111 (511) 0 5621 0 *fixed minimum delay not included table 9. examples of theoretical delay values for pd0 and pd1 in extended mode inputs: in0/in0 , in1/in1 , outputs: q0/q0 , q1, q1 extended delay mode pd0* (ps) pd1* (ps) total delay* (ps) pd1 d[8:0] (decimal) pd0 d[8:0] (decimal) msel 000000000 (0) 000000000 (0) 1 0 0 0 000000000 (0) 000000001 (1) 1 0 11 11 000000000 (0) 000000010 (2) 1 0 22 22 000000000 (0) 000000011 (3) 1 0 33 33 ? ? ? ? ? ? ? ? ? ? ? ? 000000000 (0) 111111101 (509) 1 0 5599 5599 000000000 (0) 111111110 (510) 1 0 5610 5610 000000000 (0) 111111111 (511) 1 0 5621 5621 000000001 (1) 111111111 (511) 1 11 5621 5632 000000010 (2) 111111111 (511) 1 22 5621 5643 ? ? ? ? ? ? ? ? ? ? ? ? 111111100 (508) 111111111 (511) 1 5588 5621 11209 111111101 (509) 111111111 (511) 1 5599 5621 11220 111111110 (510) 111111111 (511) 1 5610 5621 11231 111111111 (511) 111111111 (511) 1 5621 5621 11242 *fixed minimum delay not included
nb6l295 http://onsemi.com 11 figure 9. input structure 50 50 vtx vtx v cc inx inx i inx v th inx v th figure 10. differential input driven single ? ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th figure 11. v th diagram inx inx figure 12. differential inputs driven differentially v ild(max) v ihd(max) v ihd v ild v ihd(min) v ild(min) v cmr gnd v id = v ihd ? v ild v cc inx inx qx qx t pd t pd v outpp = v oh (qx) ? v ol (qx) v inpp = v ih (inx) ? v il (inx) figure 13. differential inputs driven differentially figure 14. v cmr diagram figure 15. ac reference measurement v ihd v ild v id = |v ihd(inx) ? v ild(inx)| inx inx
nb6l295 http://onsemi.com 12 gnd v cc gnd lvpecl driver 50 z o = 50 z o = 50 50 nb6l295 v cc v t x gnd v cc gnd cml driver 50 * z o = 50 z o = 50 50 * nb6l295 v t x = v t x = v cc figure 16. lvpecl interface figure 17. lvds interface v t x = v t x = v cc ? 2.0 v figure 18. cml interface, standard 50 load gnd gnd lvds driver 50 * z o = 50 z o = 50 50 * nb6l295 v t x = v t x figure 19. capacitor ? coupled differential interface (v t x/v t x connected to v refac ; v refac bypassed to ground with 0.1 f capacitor) figure 20. capacitor ? coupled single ? ended interface (v t x/v t x connected to external v refac ; v refac bypassed to ground with 0.1 f capacitor) v t x v t x v t x v t x v t x v cc v cc v cc v cc inx inx inx inx inx inx gnd v cc gnd differential driver 50 * z o = 50 z o = 50 50 * nb6l295 v t x = v t x = external v refac v t x v t x v refac v cc inx inx gnd v cc gnd 50 * z o = 50 50 * nb6l295 v t x = v t x = external v refac v t x v t x v refac v cc inx inx single ? ended driver
nb6l295 http://onsemi.com 13 driver device receiver device qd figure 21. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) q d v tt 50 50 z = 50 z = 50 v tt = v cc ? 2.0 v figure 22. output voltage amplitude (v outpp ) vs. output frequency at ambient temperature (typical) f out , clock output frequency (ghz) 1.5 1.0 0.5 0 800 v outpp , typical output voltage amplitude (mv) 700 600 500 400 300 200 100 0 2.0 ordering information device package shipping ? NB6L295MNG qfn ? 24 (pb ? free) 92 units / rail nb6l295mntxg qfn ? 24 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb6l295 http://onsemi.com 14 package dimensions qfn24, 4x4, 0.5p mn suffix case 485l ? 01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d b 0.15 c a2 a a3 a e pin 1 identification 2x 0.15 c 2x 0.08 c 0.10 c a1 c dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a2 0.60 0.80 a3 0.20 ref b 0.20 0.30 d 4.00 bsc d2 2.70 2.90 e 4.00 bsc e2 2.70 2.90 e 0.50 bsc l 0.30 0.50 24x l d2 b 1 6 7 18 13 19 e 12 e2 e 24 0.10 b 0.05 a c c ref on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 nb6l295/d eclinps max is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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